NYU Computer Architecture Day 2024
Scope
This will be an opportunity to engage and exchange ideas with fellow computer architects in an informal setting. We hope to see you there!
Date
Friday March 22, 2024 from ~10AM - 5PM.
Schedule (Tentative)
Please feel free to arrive early to NYU Tandon (location below). We will have a welcome booth setup on the first floor and there will be refreshments on the 12th floor (where the event is being held).
| Time | Event |
|---|---|
| 10:20 - 10:30 | Welcome |
| 10:30 - 11:30 | Brannon Batson - Keynote Talk |
| 11:30 - 12:30 | Student Presentations - Session 1 (Session Chair: Austin Ebel) |
| 12:30 - 2:00 | Lunch (on your own, suggestions below!) |
| 2:15 - 3:15 | Student Presentations - Session 2 (Session Chair: Negar Neda) |
| 3:15 - 3:30 | Break |
| 3:30 - 4:15 | Student Presentations - Session 3 (Session Chair: Alhad Daftardar) |
| 4:15 - 4:30 | Closing Remarks |
| 4:30 - | Socializing, drinks, dinner (on your own!) |
Keynote
Title
Using Specialized Hardware Pipelines to Massively Accelerate Molecular Dynamics Simulations in Anton 3
Abstract
At D. E. Shaw Research, we have designed and built multiple generations of highly successful special-purpose supercomputers for molecular dynamics simulations. The newest generation, Anton 3, achieves simulation speeds at least 100-fold faster than any other currently available supercomputer on a wide range of biomolecular systems. Anton machines are an essential foundational technology for our scientific and drug discovery efforts. This talk will describe how we co-design hardware, software, and algorithms to accelerate both research and drug discovery, focusing on how specialized hardware pipelines contribute to the enormous speedups that Anton machines achieve.
Speaker Bio
Brannon Batson has been a hardware design engineer at D. E. Shaw Research since 2005, contributing to the design of all Anton machines to date. His focus is on the specialized arithmetic pipelines. This role includes high-level architecture, performance modeling, microarchitecture, numerical analysis, and physical design.
Brannon received a B.S. in computer engineering and an M.S. in electrical engineering from Purdue University. Prior to joining D. E. Shaw Research, Brannon was a Senior Hardware Engineer at Intel Corporation, where he was a member of the lead architecture group for a next-generation processor and the lead inventor of the QuickPath Interconnect (QPI) cache coherency protocol.
Student Presentations
Session 1:
| Name | Affiliation | Title |
|---|---|---|
| Muhammed Ugur | Yale University | Swapping-Centric Neural Interfaces |
| Harry Liu | Columbia University | Micro-architectural Characterization and Optimization of Protocol Buffers |
| Ranyang Zhou | New Jersey Institute of Technology | DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks |
| Kaustubh Shivdikar | Northeastern University | Micro-architectural extensions for AMD GPUs to accelerate Large Language Models |
| Hengrui Zhang | Princeton University | LLMCompass: A Hardware Evaluation Framework for LLM Workloads |
| Jianqiao Mo | New York University | HAAC: A Hardware-software Co-design to Accelerate Garbled Circuits |
Session 2:
| Name | Affiliation | Title |
|---|---|---|
| Kaifeng Xu | Princeton University | Temporal Branch Predictor Prefetching for Serverless Invocations |
| Joseph Zuckerman | Columbia University | EPOCHS-1: A Case-Study in Collaborative System-on-Chip Design with ESP |
| Deniz Najafi / Mehrdad Morsali | New Jersey Institute of Technology | OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing |
| Nisarg Ujjainkar | University Of Rochester | Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality |
| Adam Hastings | Columbia University | FAIRSHARE: Measuring Security Overheads On-Device and In Situ |
| Jian Zhang | Rutgers University | OmniCache: Collaborative Caching for Near-storage Accelerators |
Session 3:
| Name | Affiliation | Title |
|---|---|---|
| August Ning | Princeton University | Chip Architectures Under Advanced Computing Sanctions |
| Rohan Baskar Prabhakar | Princeton University | System Aware Transformer Model Design |
| Haiyue Ma | Princeton University | A Hardware AI Kill Switch |
| Anthony Etim | Yale University | Covert Channels in FPGA-enabled SmartSSDs |
RSVP Form
https://forms.gle/zn9gp8bZMMHKgC1P6 (Closed)
Location
This event will be held at the Electrical and Computer Engineering Department at NYU Tandon in Downtown Brooklyn.
Address:
370 Jay St, 12 Floor,
Brooklyn, NY 11201.
Direction:
- From JFK Airport: take the AirTrain to Howard Beach Station, then transfer to the subway A line (Manhattan-bound) and get off at Jay St-MetroTech Station.
- From LaGuardia (LGA) Airport: take the Q70-SBS bus to Roosevelt Av/74 St Station, then take the subway F line (Manhattan/Brooklyn-bound) and get off at Jay St-MetroTech Station.
- From Newark Airport: take the Newark Airport Express Shuttle to Bryant Park, then take the subway F line (Brooklyn-bound) and get off at Jay St-MetroTech Station. Alternative options include AirTrain and NJ Transit.
- (Railroad) From NY Penn Station: take the subway A/C line (Brooklyn-bound) and get off at Jay St-MetroTech Station.
Food Options
There are two food halls close to NYU that offer a variety of cuisines:
We are also only two stops away (via the F line) from Chinatown (Directions]
There are also plenty of restaurants around NYU on Atlantic Avenue, Court Street, and Smith Street (Map)